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| 1/39 www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. system led drivers for mobile phones 7x17(max.) dot matrix led display driver bd26502gul description bd26502gul is ?matrix led driver? that is the most suitable for the cellular phone. it can control 7x17(119 dot) led matrix by internal 7-channel pmos sws and 17-channel led drivers. it can control the luminance and firefl y lighting of the led matrix by th e setting of the internal register. it supports spi and i2c interface. vcsp50l4 (4.1mm 0.55mm height max), small and thin type chip size package. it adopts the very thin csp package that is the most suitable for the slim phone. features 1) led matrix driver (7x17) ? it has 7-channel pmos sws and 17-channel current drivers with 1/7 timing driven sequentially. ? put on/off(for every dot). ? the current drivers can drive 0-20.00ma current with 16 step(for every dot). ? 64 steps of the luminance control by pwm (common setting for all dots) ? continuous (tdma off ) lighting function for led14-led17 ? easy register setting by a/b 2-side map for each dot. 2) automatic slope function ? cycle time, slope time can be set for each dot. 3) 8-direction automatic scroll function. 4) interface ?spi and i 2 c bus fs mode(max 400khz)compatibility ? for i 2 c mode, i 2 c device address is selectable (74h or 75h) 5) thermal shutdown 6) small and thin csp package ? 62pin vcsp50l4(4.1mm 2 0.55mm height max) *this chip is not designed to protect itself against radioactive rays. *this material may be changed on its way to designing. *this material is not the official specification. absolute maximum ratings (ta=25 o c) parameter symbol ratings unit maximum voltage (note2) vmax 7 v maximum voltage (note1) viomax 4.5 v power dissipation (note3) pd 1550 mw operating temperature range topr -40 ~ +85 storage temperature range tstg -55 ~ +150 note1) vio,resetb,ce,sda,scl,ifm ode,sync,clki n,clkout,test1,test2,test 3,testo, do terminal note2) except the above note3) power dissipation deleting is 12.4mw/ o c , when it?s used in over 25 o c. (rohm?s standard board has been mounted.) the power dissipation of the ic has to be less than the one of the package. operating conditions (vbat vio, vinsw vbat, ta=-40~85 o c) parameter symbol limits unit vbat input voltage vbat 2.7 ~ 5.5 v vinsw input voltage vinsw 2.7 ~ 5.5 v vio pin voltage vio 1.65 ~ 3.3 v no.10041eat01
technical note 2/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. electrical characteristics (unless otherwise specifi ed, ta=25c, vbat=3.6v, vinsw=3.6v, vio=1.8v) parameter symbol limit unit condition min. typ. max. [ circuit current ] vbat circuit current 1 ibat1 - 0 3.0 a resetb=0v, vio=0v vbat circuit current 2 ibat2 - 0.8 5.0 a resetb=0v, vio=1.8v vbat circuit current 3 ibat3 - 2.0 3.5 ma when led1-17 are active with default settings. [ uvlo ] uvlo threshold vuvlo - 2.1 2.5 v vbat falling uvlo hysteresis vhyuvlo 50 - - mv [ led driver ] (led1-17) maximum output current iled max - 20.00 - ma led1-17 ,iset 100k output current iled -7.0% 10.67 +7.0% ma i=10.67ma setting, vled=1v led current matching iledmt - - 5 % iledmt= (iledmax-iledmin)/(iledmax+iledmin) i=10.67ma setting, vled=1v driver pin voltage range vled 0.2 - vbat- 1.4 v led off leak current ilkled - - 1.0 a [ pmos switch ] leak current at off ileakp - - 1.0 a resistor at on ronp - 1.0 - ? isw=170ma, vinsw=4.5v [ osc ] osc frequency fosc 0.96 1.2 1.44 mhz [ ce, sync, clkin, ifmode ] l level input voltage vil1 -0.3 - 0.25 x vio v h level input voltage vih1 0.75 x vio - vio +0.3 v l level input current iil1 - 0 1 a h level input current iih1 - 0 1 a [ sda, scl ] l level input voltage vil2 -0.3 - 0.25 x vio v h level input voltage vih2 0.75 x vio - vio +0.3 v input hysteresis vhys 0.05 x vio - - v l level output voltage (for sda pin) vol2 0 - 0.3 v at 3ma sink current input current iin1 -3 - 3 a input voltage = from (0.1 x vio) to (0.9 x vio) [ resetb ] l level input voltage vil3 -0.3 - 0.25 x vio v h level input voltage vih3 0.75 x vio - vio +0.3 v input current iin2 - 0 1 a input voltage = from (0.1 x vio) to (0.9 x vio) [ clkout ] l level output voltage vol1 - - 0.4 v iol=2ma h level output voltage voh1 0.75 x vio - - v ioh=-2ma technical note 3/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. power dissipation (on the rohm?s standard board) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 150 ta( ) power dissipation pd w) 1550mw fig.1 information of the rohm?s standard board material: glass-epoxy size : 50mm 58mm 1.75mm( 8 th layer ) wiring pattern figure refer to after page. , technical note 4/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. block diagram / application circuit example 1 fig.2 block diagram / application circuit example 1 pwm led1 tdma tdma led2 tdma led3 tdma led4 tdma led5 tdma led6 tdma tdma led8 tdma led9 tdma led10 tdma led11 tdma tdma led13 led12 led7 tdma led14 tdma led15 tdma tdma led17 led16 sw1 t00 sw2 t01 sw3 t02 t03 t04 t05 t06 sw4 sw5 sw6 sw7 10 f vref iref resetb ce sd a scl ifmode sync clkin clkout logic tdma i2c or spi selectable 7 17 dot matrix unit iset 100k technical note 6/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. pin arrangement bottom view h test4 led11 led12 gnd1 led15 led16 led17 testo g led9 led10 led13 led14 gnd2 clkout ce sda f led8 iset ledgnd3 ledgnd4 test1 ifmode scl vio e ledgnd2 led7 vbat1 vbat2 resetb clkin sync do d led5 led6 led4 sw3 sw2 sw1 vinsw1 c led3 ledgnd1 gnd3 test2 sw5 sw4 vinsw2 b led2 led1 gnd4 gnd5 gnd6 sw6 sw7 vinsw3 a test3 vbat3 gnd7 gnd8 gnd9 gnd10 gnd11 test5 1 2 3 4 5 6 7 8 index total 62 balls technical note 7/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. package 62pin vcsp50l4 csp small package size : 4.10mm height : 0.55mm max a ball pitch : 0.5 mm *index post has no solder ball technical note 8/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. pin functions no ball no. pin name i/o pull down unused terminal setting esd diode functions equivalent circuit for power for ground 1 a1 test3 i 94k ? gnd vio gnd test input pin 3 e 2 a2 vbat3 - - vbat - gnd battery is connected a 3 a3 gnd7 - - gnd vbat - ground b 4 a4 gnd8 - - gnd vbat - ground b 5 a5 gnd9 - - gnd vbat - ground b 6 a6 gnd10 - - gnd vbat - ground b 7 a7 gnd11 - - gnd vbat - ground b 8 a8 test5 i - gnd vinsw gnd test input pin 5 i 9 b1 led2 o - gnd - gnd led2 driver output k 10 b2 led1 o - gnd - gnd led1 driver output k 11 b3 gnd4 - - gnd vbat - ground b 12 b4 gnd5 - - gnd vbat - ground b 13 b5 gnd6 - - gnd vbat - ground b 14 b6 sw6 o - vinsw vinsw gnd p-mos sw6 output c 15 b7 sw7 o - vinsw vinsw gnd p-mos sw7 output c 16 b8 vinsw3 - - vinsw - gnd power supply for sw1-7 a 17 c1 led3 o - gnd - gnd led3 driver output k 18 c2 ledgnd1 - - gnd vbat - ground b 19 c4 gnd3 - - gnd vbat - ground b 20 c5 test2 i 94k ? gnd vio gnd test input pin 2 e 21 c6 sw5 o - vinsw vinsw gnd p-mos sw output c 22 c7 sw4 o - vinsw vinsw gnd p-mos sw4 output c 23 c8 vinsw2 - - vinsw - gnd power supply for sw1-7 a 24 d1 led5 o - gnd - gnd led5 driver output k 25 d2 led6 o - gnd - gnd led6 driver output k 26 d3 led4 o - gnd - gnd led4 driver output k 27 d5 sw3 o - vinsw vinsw gnd p-mos sw3 output c 28 d6 sw2 o - vinsw vinsw gnd p-mos sw2 output c 29 d7 sw1 o - vinsw vinsw gnd p-mos sw1output c 30 d8 vinsw1 - - vinsw - gnd power supply for sw1-7 a 31 e1 ledgnd2 - - gnd vbat - ground b 32 e2 led7 o - gnd - gnd led7 driver output k 33 e3 vbat1 - - vbat - gnd battery is connected a 34 e4 vbat2 - - vbat - gnd battery is connected a 35 e5 resetb i - gnd vio gnd reset in put pin (l: reset, h: reset cancel) d 36 e6 clkin i - gnd vio gnd external clk input pin d 37 e7 sync i - gnd vio gnd external synchronous input pin d 38 e8 do o - open vio gnd test output pin2 g 39 f1 led8 o - gnd - gnd led8 driver output k 40 f2 iset i - open vbat gnd led constant current driver current setting pin j 41 f3 ledgnd3 - - gnd vbat - ground b 42 f4 ledgnd4 - - gnd vbat - ground b 43 f5 test1 i 94k ? gnd vio gnd test input pin 1 e 44 f6 ifmode i - gnd vio gnd i 2 c/spi select pin (l: i 2 c, h: spi) d 45 f7 scl i - gnd vio gnd spi, i 2 c clk input pin d technical note 9/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. no ball no. pin name i/o pull down unused terminal setting esd diode functions equivalent circuit for power for ground 46 f8 vio - - vio - gnd i/o power supply is connected a 47 g1 led9 o - gnd - gnd led9 driver output k 48 g2 led10 o - gnd - gnd led10 driver output k 49 g3 led13 o - gnd - gnd led13 driver output k 50 g4 led14 o - gnd - gnd led14 driver output k 51 g5 gnd2 - - gnd vbat - ground b 52 g6 clkout o - open vio gnd reference clk output pin g 53 g7 ce i - gnd vio gnd spi enable pin(h:enable), o r i 2 c slave address selection (l: 74h, h: 75h) d 54 g8 sda i/o - gnd vio gnd spi data input / i2c data input-output pin f 55 h1 test4 i - gnd vbat gnd test input pin 4 h 56 h2 led11 o - gnd - gnd led11 driver output k 57 h3 led12 o - gnd - gnd led12 driver output k 58 h4 gnd1 - - gnd vbat - ground b 59 h5 led15 o - gnd - gnd led15 driver output k 60 h6 led16 o - gnd - gnd led16 driver output k 61 h7 led17 o - gnd - gnd led17 driver output k 62 h8 testo o - open vio gnd test output pin1 g * please connect the unused led pins to the ground. * it is prohibition to set the registers for unused led. total 62 pins equivalent circuit a vbat b vinsw i vio vio d vbat j vinsw c vinsw vio g vio vio vio e vio vio f vbat h k technical note 10/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. serial interface 1. spi format ? when ifmode is set to ?h?, it can interface with spi format. ? the serial interface is four terminals (serial clock termi nal (scl), serial data inpu t terminal (sda), and chip selection input terminal (ce)). (1)write operation ? data is taken into an internal shift register with rising edge of clk. (max of the frequency is 13mhz.) ? the receive data becomes enable in the ?h? section of ce. (active ?h?.) ? the transmit data is forwarded (with msb-first) in the order of write command ?0?(1bit), t he control register address (7bit) and data (8bit). ce scl sda w a6 a5 a4 a3 a2 a1 a0 d4 d3 d2 d1 d0 d7 d6 d5 fig.4 writing format (2)timing diagram twlc ce scl sda tcsw twhc tcss tscyc tss tsh tcgh fig.5 timing diagram (spi format) (3) electrical characteristics (unless otherwise s pecified, ta=25c, vbat=3.6v, vinsw=3.6v, vio=1.8v) parameter symbol limit unit condition min typ max scl cycle time tscyc 76 - - ns h period of scl cycle twhc 35 - - ns l period of scl cycle twlc 35 - - ns sda setup time tss 38 - - ns sda hold time tsh 38 - - ns read and write interval tcsw 38 - - ns ce setup time tcss 55 - - ns ce hold time tcgh 55 - - ns technical note 11/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 2. i 2 c bus format when ifmode is set to ?l?, it can interface with i 2 c bus format. (1) slave address ce a7 a6 a5 a4 a3 a2 a1 r/w l 1 1 1 0 1 0 0 0 h 1 1 1 0 1 0 1 (2) bit transfer scl transfers 1-bit data during h. during h of scl, sda c annot be changed at the time of bit transfer. if sda changes while scl is h, start conditions or stop conditions will occur and it will be interpreted as a control signal. sda scl sda a state of stability data are effective sda it can change fig.6 bit transfer (i 2 c format) (3) start and stop condition when sda and scl are h, data is not transferred on the i 2 c- bus. this condition indicates, if sda changes from h to l while scl has been h, it will become start (s) conditions, and an access start, if sda changes from l to h while scl has been h, it will become stop (p) conditions and an access end. sda scl s p start condition stop condition fig.7 start/stop condition (i 2 c format) (4) acknowledge it transfers data 8 bits each after the occurrence of start condition. a transmitter opens sda after transfer 8bits data, and a receiver returns the acknowledge signal by setting sda to l. 12 89 data output by transmitter data output by receiver acknowledge not acknowledge s start condition clock pulse for acknowledgement scl fig.8 acknowledge (i 2 c format) technical note 12/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. (5) writing protocol a register address is transferred by the next 1 byte that transferred the slave address and the write-in command. the 3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is carried out automatically. however, when a register address turns into the last address (77h), it is set to 00h by the next transmission. after the transmission end, the increment of the address is carried out. s a a a p register address slave address from master to slave from slave to master r/w=0(write) data a d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 x x x x x x x *1 *1 data a =acknowledge(sd a low) a =not acknowledge(sda high) s=start condition p=stop condition *1: write timing register address increment register address increment (6) timing diagram sda s cl t su;dat t low s sr p s t buf t hd;sta t su;sta t high t hd;sta t hd;dat t su;sto fig.9 timing diagram (i2c format) (7) electrical characteristics(unless otherwise specified, ta=25 o c, vbat=3.6v, vinsw=3.6v, vio=1.8v) parameter symbol standard-mode fast-mode unit min. typ. max. min. typ. max. i 2 c bus format scl clock frequency f scl 0 - 100 0 - 400 khz low period of the scl clock t low 4.7 - - 1.3 - - s high period of the scl clock t high 4.0 - - 0.6 - - s hold time (repeated) start condition after this period, the first clock is generated t hd;sta 4.0 - - 0.6 - - s set-up time for a repeated start condition t su;sta 4.7 - - 0.6 - - s data hold time t hd;dat 0 - 3.45 0 - 0.9 s data set-up time t su;dat 250 - - 100 - - ns set-up time for stop condition t su;sto 4.0 - - 0.6 - - s bus free time between a stop and start condition t buf 4.7 - - 1.3 - - s technical note 13/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. register list * please be sure to write ?0? in the register which is not assigned. * it is prohibition to write data to the address which is not assigned. control register a ddress default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 00h 00h - - - - - - - sftrst reset w software reset 01h 00h - - - - oscen - - - osc w osc on/off control 11h 00h - - led6on led5on led4on led3on led2on led1on led driver w led1-6 enable 12h 00h - - led12on led11on le d10on led9on led8on led7on w led7-12 enable 13h 00h - - - led17on led16on led15on led14on led13on w led13-17 enable 17h 0fh - - - - led17 tdmaon led16 tdmaon led15 tdmaon led14 tdmaon w led14-17 tdma enable 20h 00h - - pwmset[5:0] pwm w led1-17pwm dutysetting 21h 00h - - - - syncact syncon clkout clkin clk w clk selection, sync operation control 2dh 00h - - - - - pwmen slpen sclen matrix w pwm,slope,scroll on/off setting 2eh 00h - - - - - - - sclrst w reset scroll 2fh 00h - sclspeed[2:0] up down right left w scroll setting 30h 00h - - - - - - - start w led matrix control 31h 00h - - - - - - clrb clra w matrix data clear 7fh 00h - - - - - iab oab rmcg rmap w resister map change technical note 14/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. a-pattern register address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 01h 08h scyca00[1:0] sdlya00[1:0] ileda00set[3:0] matrix data w data for matrix 00(da00) 02h 08h scyca01[1:0] sdlya01[1:0] ileda01set[3:0] w data for matrix 01(da01) 03h 08h scyca02[1:0] sdlya02[1:0] ileda02set[3:0] w data for matrix 02(da02) 04h 08h scyca03[1:0] sdlya03[1:0] ileda03set[3:0] w data for matrix 03(da03) 05h 08h scyca04[1:0] sdlya04[1:0] ileda04set[3:0] w data for matrix 04(da04) 06h 08h scyca05[1:0] sdlya05[1:0] ileda05set[3:0] w data for matrix 05(da05) 07h 08h scyca06[1:0] sdlya06[1:0] ileda06set[3:0] w data for matrix 06(da06) 08h 08h scyca10[1:0] sdlya10[1:0] ileda10set[3:0] w data for matrix 10(da10) 09h 08h scyca11[1:0] sdlya11[1:0] ileda11set[3:0] w data for matrix 11(da11) 0ah 08h scyca12[1:0] sdlya12[1:0] ileda12set[3:0] w data for matrix 12(da12) 0bh 08h scyca13[1:0] sdlya13[1:0] ileda13set[3:0] w data for matrix 13(da13) 0ch 08h scyca14[1:0] sdlya14[1:0] ileda14set[3:0] w data for matrix 14(da14) 0dh 08h scyca15[1:0] sdlya15[1:0] ileda15set[3:0] w data for matrix 15(da15) 0eh 08h scyca16[1:0] sdlya16[1:0] ileda16set[3:0] w data for matrix 16(da16) 0fh 08h scyca20[1:0] sdlya20[1:0] ileda20set[3:0] w data for matrix 20(da20) 10h 08h scyca21[1:0] sdlya21[1:0] ileda21set[3:0] w data for matrix 21(da21) 11h 08h scyca22[1:0] sdlya22[1:0] ileda22set[3:0] w data for matrix 22(da22) 12h 08h scyca23[1:0] sdlya23[1:0] ileda23set[3:0] w data for matrix 23(da23) 13h 08h scyca24[1:0] sdlya24[1:0] ileda24set[3:0] w data for matrix 24(da24) 14h 08h scyca25[1:0] sdlya25[1:0] ileda25set[3:0] w data for matrix 25(da25) 15h 08h scyca26[1:0] sdlya26[1:0] ileda26set[3:0] w data for matrix 26(da26) 16h 08h scyca30[1:0] sdlya30[1:0] ileda30set[3:0] w data for matrix 30(da30) 17h 08h scyca31[1:0] sdlya31[1:0] ileda31set[3:0] w data for matrix 31(da31) 18h 08h scyca32[1:0] sdlya32[1:0] ileda32set[3:0] w data for matrix 32(da32) 19h 08h scyca33[1:0] sdlya33[1:0] ileda33set[3:0] w data for matrix 33(da33) 1ah 08h scyca34[1:0] sdlya34[1:0] ileda34set[3:0] w data for matrix 34(da34) 1bh 08h scyca35[1:0] sdlya35[1:0] ileda35set[3:0] w data for matrix 35(da35) 1ch 08h scyca36[1:0] sdlya36[1:0] ileda36set[3:0] w data for matrix 36(da36) 1dh 08h scyca40[1:0] sdlya40[1:0] ileda40set[3:0] w data for matrix 40(da40) 1eh 08h scyca41[1:0] sdlya41[1:0] ileda41set[3:0] w data for matrix 41(da41) 1fh 08h scyca42[1:0] sdlya42[1:0] ileda42set[3:0] w data for matrix 42(da42) 20h 08h scyca43[1:0] sdlya43[1:0] ileda43set[3:0] w data for matrix 43(da43) 21h 08h scyca44[1:0] sdlya44[1:0] ileda44set[3:0] w data for matrix 44(da44) 22h 08h scyca45[1:0] sdlya45[1:0] ileda45set[3:0] w data for matrix 45(da45) 23h 08h scyca46[1:0] sdlya46[1:0] ileda46set[3:0] w data for matrix 46(da46) 24h 08h scyca50[1:0] sdlya50[1:0] ileda50set[3:0] w data for matrix 50(da50) 25h 08h scyca51[1:0] sdlya51[1:0] ileda51set[3:0] w data for matrix 51(da51) 26h 08h scyca52[1:0] sdlya52[1:0] ileda52set[3:0] w data for matrix 52(da52) 27h 08h scyca53[1:0] sdlya53[1:0] ileda53set[3:0] w data for matrix 53(da53) 28h 08h scyca54[1:0] sdlya54[1:0] ileda54set[3:0] w data for matrix 54(da54) 29h 08h scyca55[1:0] sdlya55[1:0] ileda55set[3:0] w data for matrix 55(da55) 2ah 08h scyca56[1:0] sdlya56[1:0] ileda56set[3:0] w data for matrix 56(da56) 2bh 08h scyca60[1:0] sdlya60[1:0] ileda60set[3:0] w data for matrix 60(da60) 2ch 08h scyca61[1:0] sdlya61[1:0] ileda61set[3:0] w data for matrix 61(da61) 2dh 08h scyca62[1:0] sdlya62[1:0] ileda62set[3:0] w data for matrix 62(da62) 2eh 08h scyca63[1:0] sdlya63[1:0] ileda63set[3:0] w data for matrix 63(da63) 2fh 08h scyca64[1:0] sdlya64[1:0] ileda64set[3:0] w data for matrix 64(da64) 30h 08h scyca65[1:0] sdlya65[1:0] ileda65set[3:0] w data for matrix 65(da65) technical note 15/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 31h 08h scyca66[1:0] sdlya66[1:0] ileda66set[3:0] matrix data w data for matrix 66(da66) 32h 08h scyca70[1:0] sdlya70[1:0] ileda 70set[3:0] w data for matrix 70(da70) 33h 08h scyca71[1:0] sdlya71[1:0] ileda 71set[3:0] w data for matrix 71(da71) 34h 08h scyca72[1:0] sdlya72[1:0] ileda 72set[3:0] w data for matrix 72(da72) 35h 08h scyca73[1:0] sdlya73[1:0] ileda 73set[3:0] w data for matrix 73(da73) 36h 08h scyca74[1:0] sdlya74[1:0] ileda 74set[3:0] w data for matrix 74(da74) 37h 08h scyca75[1:0] sdlya75[1:0] ileda 75set[3:0] w data for matrix 75(da75) 38h 08h scyca76[1:0] sdlya76[1:0] ileda 76set[3:0] w data for matrix 76(da76) 39h 08h scyca80[1:0] sdlya80[1:0] ileda 80set[3:0] w data for matrix 80(da80) 3ah 08h scyca81[1:0] sdlya81[1:0] ileda 81set[3:0] w data for matrix 81(da81) 3bh 08h scyca82[1:0] sdlya82[1:0] ileda 82set[3:0] w data for matrix 82(da82) 3ch 08h scyca83[1:0] sdlya83[1:0] ileda 83set[3:0] w data for matrix 83(da83) 3dh 08h scyca84[1:0] sdlya84[1:0] ileda 84set[3:0] w data for matrix 84(da84) 3eh 08h scyca85[1:0] sdlya85[1:0] ileda 85set[3:0] w data for matrix 85(da85) 3fh 08h scyca86[1:0] sdlya86[1:0] ileda 86set[3:0] w data for matrix 86(da86) 40h 08h scyca90[1:0] sdlya90[1:0] ileda 90set[3:0] w data for matrix 90(da90) 41h 08h scyca91[1:0] sdlya91[1:0] ileda 91set[3:0] w data for matrix 91(da91) 42h 08h scyca92[1:0] sdlya92[1:0] ileda 92set[3:0] w data for matrix 92(da92) 43h 08h scyca93[1:0] sdlya93[1:0] ileda 93set[3:0] w data for matrix 93(da93) 44h 08h scyca94[1:0] sdlya94[1:0] ileda 94set[3:0] w data for matrix 94(da94) 45h 08h scyca95[1:0] sdlya95[1:0] ileda 95set[3:0] w data for matrix 95(da95) 46h 08h scyca96[1:0] sdlya96[1:0] ileda 96set[3:0] w data for matrix 96(da96) 47h 08h scycaa0[1:0] sdlyaa0[1:0] iledaa0 set[3:0] w data fo r matrix a0(daa0) 48h 08h scycaa1[1:0] sdlyaa1[1:0] iledaa1 set[3:0] w data fo r matrix a1(daa1) 49h 08h scycaa2[1:0] sdlyaa2[1:0] iledaa2 set[3:0] w data fo r matrix a2(daa2) 4ah 08h scycaa3[1:0] sdlyaa3[1:0] iledaa3 set[3:0] w data fo r matrix a3(daa3) 4bh 08h scycaa4[1:0] sdlyaa4[1:0] iledaa4 set[3:0] w data fo r matrix a4(daa4) 4ch 08h scycaa5[1:0] sdlyaa5 [1:0] iledaa5set[3:0] w da ta for matrix a5(daa5) 4dh 08h scycaa6[1:0] sdlyaa6 [1:0] iledaa6set[3:0] w da ta for matrix a6(daa6) 4eh 08h scycab0[1:0] sdlyab0[1:0] iledab0 set[3:0] w data fo r matrix b0(dab0) 4fh 08h scycab1[1:0] sdlyab1[1:0] iledab1 set[3:0] w data fo r matrix b1(dab1) 50h 08h scycab2[1:0] sdlyab2[1:0] iledab2 set[3:0] w data fo r matrix b2(dab2) 51h 08h scycab3[1:0] sdlyab3[1:0] iledab3 set[3:0] w data fo r matrix b3(dab3) 52h 08h scycab4[1:0] sdlyab4[1:0] iledab4 set[3:0] w data fo r matrix b4(dab4) 53h 08h scycab5[1:0] sdlyab5[1:0] iledab5 set[3:0] w data fo r matrix b5(dab5) 54h 08h scycab6[1:0] sdlyab6[1:0] iledab6 set[3:0] w data fo r matrix b6(dab6) 55h 08h scycac0[1:0] sdlyac0[1:0] iledac 0set[3:0] w data fo r matrix c0(dac0) 56h 08h scycac1[1:0] sdlyac1[1:0] iledac 1set[3:0] w data fo r matrix c1(dac1) 57h 08h scycac2[1:0] sdlyac2[1:0] iledac 2set[3:0] w data fo r matrix c2(dac2) 58h 08h scycac3[1:0] sdlyac3[1:0] iledac 3set[3:0] w data fo r matrix c3(dac3) 59h 08h scycac4[1:0] sdlyac4[1:0] iledac 4set[3:0] w data fo r matrix c4(dac4) 5ah 08h scycac5[1:0] sdlyac5[1:0] iledac 5set[3:0] w data fo r matrix c5(dac5) 5bh 08h scycac6[1:0] sdlyac6[1:0] iledac 6set[3:0] w data fo r matrix c6(dac6) 5ch 08h scycad0[1:0] sdlyad0[1:0] iledad 0set[3:0] w data fo r matrix d0(dad0) 5dh 08h scycad1[1:0] sdlyad1[1:0] iledad 1set[3:0] w data fo r matrix d1(dad1) 5eh 08h scycad2[1:0] sdlyad2[1:0] iledad 2set[3:0] w data fo r matrix d2(dad2) 5fh 08h scycad3[1:0] sdlyad3[1:0] iledad 3set[3:0] w data fo r matrix d3(dad3) 60h 08h scycad4[1:0] sdlyad4[1:0] iledad 4set[3:0] w data fo r matrix d4(dad4) technical note 16/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 61h 08h scycad5[1:0] sdlyad5[1:0] iledad5set[3:0] matrix data w data for matrix d5(dad5) 62h 08h scycad6[1:0] sdlyad6[1:0] iledad 6set[3:0] w data fo r matrix d6(dad6) 63h 08h scycae0[1:0] sdlyae0[1:0] iledae0 set[3:0] w data fo r matrix e0(dae0) 64h 08h scycae1[1:0] sdlyae1[1:0] iledae1 set[3:0] w data fo r matrix e1(dae1) 65h 08h scycae2[1:0] sdlyae2[1:0] iledae2 set[3:0] w data fo r matrix e2(dae2) 66h 08h scycae3[1:0] sdlyae3[1:0] iledae3 set[3:0] w data fo r matrix e3(dae3) 67h 08h scycae4[1:0] sdlyae4[1:0] iledae4 set[3:0] w data fo r matrix e4(dae4) 68h 08h scycae5[1:0] sdlyae5[1:0] iledae5 set[3:0] w data fo r matrix e5(dae5) 69h 08h scycae6[1:0] sdlyae6[1:0] iledae6 set[3:0] w data fo r matrix e6(dae6) 6ah 08h scycaf0[1:0] sdlyaf0[1:0] iledaf 0set[3:0] w data for matrix f0(daf0) 6bh 08h scycaf1[1:0] sdlyaf1[1:0] iledaf 1set[3:0] w data for matrix f1(daf1) 6ch 08h scycaf2[1:0] sdlyaf2[1:0] iledaf 2set[3:0] w data for matrix f2(daf2) 6dh 08h scycaf3[1:0] sdlyaf3[1:0] iledaf 3set[3:0] w data for matrix f3(daf3) 6eh 08h scycaf4[1:0] sdlyaf4[1:0] iledaf 4set[3:0] w data for matrix f4(daf4) 6fh 08h scycaf5[1:0] sdlyaf5[1:0] iledaf 5set[3:0] w data for matrix f5(daf5) 70h 08h scycaf6[1:0] sdlyaf6[1:0] iledaf 6set[3:0] w data for matrix f6(daf6) 71h 08h scycag0[1:0] sdlyag0[1:0] iledag 0set[3:0] w data for matrix g0(dag0) 72h 08h scycag1[1:0] sdlyag1[1:0] iledag 1set[3:0] w data for matrix g1(dag1) 73h 08h scycag2[1:0] sdlyag2[1:0] iledag 2set[3:0] w data for matrix g2(dag2) 74h 08h scycag3[1:0] sdlyag3[1:0] iledag 3set[3:0] w data for matrix g3(dag3) 75h 08h scycag4[1:0] sdlyag4[1:0] iledag 4set[3:0] w data for matrix g4(dag4) 76h 08h scycag5[1:0] sdlyag5[1:0] iledag 5set[3:0] w data for matrix g5(dag5) 77h 08h scycag6[1:0] sdlyag6[1:0] iledag 6set[3:0] w data for matrix g6(dag6) technical note 17/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. b-pattern register address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 01h 08h scycb00[1:0] sdlyb00[1:0] iledb00set[3:0] matrix data w data for matrix 00(db00) 02h 08h scycb01[1:0] sdlyb01[1:0] iledb 01set[3:0] w data for matrix 01(db01) 03h 08h scycb02[1:0] sdlyb02[1:0] iledb 02set[3:0] w data for matrix 02(db02) 04h 08h scycb03[1:0] sdlyb03[1:0] iledb 03set[3:0] w data for matrix 03(db03) 05h 08h scycb04[1:0] sdlyb04[1:0] iledb 04set[3:0] w data for matrix 04(db04) 06h 08h scycb05[1:0] sdlyb05[1:0] iledb 05set[3:0] w data for matrix 05(db05) 07h 08h scycb06[1:0] sdlyb06[1:0] iledb 06set[3:0] w data for matrix 06(db06) 08h 08h scycb10[1:0] sdlyb10[1:0] iledb 10set[3:0] w data for matrix 10(db10) 09h 08h scycb11[1:0] sdlyb11[1:0] iledb1 1set[3:0] w data for matrix 11(db11) 0ah 08h scycb12[1:0] sdlyb12[1:0] iledb 12set[3:0] w data for matrix 12(db12) 0bh 08h scycb13[1:0] sdlyb13[1:0] iledb 13set[3:0] w data for matrix 13(db13) 0ch 08h scycb14[1:0] sdlyb14[1:0] iledb 14set[3:0] w data for matrix 14(db14) 0dh 08h scycb15[1:0] sdlyb15[1:0] iledb 15set[3:0] w data for matrix 15(db15) 0eh 08h scycb16[1:0] sdlyb16[1:0] iledb 16set[3:0] w data for matrix 16(db16) 0fh 08h scycb20[1:0] sdlyb20[1:0] iledb 20set[3:0] w data for matrix 20(db20) 10h 08h scycb21[1:0] sdlyb21[1:0] iledb 21set[3:0] w data for matrix 21(db21) 11h 08h scycb22[1:0] sdlyb22[1:0] iledb 22set[3:0] w data for matrix 22(db22) 12h 08h scycb23[1:0] sdlyb23[1:0] iledb 23set[3:0] w data for matrix 23(db23) 13h 08h scycb24[1:0] sdlyb24[1:0] iledb 24set[3:0] w data for matrix 24(db24) 14h 08h scycb25[1:0] sdlyb25[1:0] iledb 25set[3:0] w data for matrix 25(db25) 15h 08h scycb26[1:0] sdlyb26[1:0] iledb 26set[3:0] w data for matrix 26(db26) 16h 08h scycb30[1:0] sdlyb30[1:0] iledb 30set[3:0] w data for matrix 30(db30) 17h 08h scycb31[1:0] sdlyb31[1:0] iledb 31set[3:0] w data for matrix 31(db31) 18h 08h scycb32[1:0] sdlyb32[1:0] iledb 32set[3:0] w data for matrix 32(db32) 19h 08h scycb33[1:0] sdlyb33[1:0] iledb 33set[3:0] w data for matrix 33(db33) 1ah 08h scycb34[1:0] sdlyb34[1:0] iledb 34set[3:0] w data for matrix 34(db34) 1bh 08h scycb35[1:0] sdlyb35[1:0] iledb 35set[3:0] w data for matrix 35(db35) 1ch 08h scycb36[1:0] sdlyb36[1:0] iledb 36set[3:0] w data for matrix 36(db36) 1dh 08h scycb40[1:0] sdlyb40[1:0] iledb 40set[3:0] w data for matrix 40(db40) 1eh 08h scycb41[1:0] sdlyb41[1:0] iledb 41set[3:0] w data for matrix 41(db41) 1fh 08h scycb42[1:0] sdlyb42[1:0] iledb 42set[3:0] w data for matrix 42(db42) 20h 08h scycb43[1:0] sdlyb43[1:0] iledb 43set[3:0] w data for matrix 43(db43) 21h 08h scycb44[1:0] sdlyb44[1:0] iledb 44set[3:0] w data for matrix 44(db44) 22h 08h scycb45[1:0] sdlyb45[1:0] iledb 45set[3:0] w data for matrix 45(db45) 23h 08h scycb46[1:0] sdlyb46[1:0] iledb 46set[3:0] w data for matrix 46(db46) 24h 08h scycb50[1:0] sdlyb50[1:0] iledb 50set[3:0] w data for matrix 50(db50) 25h 08h scycb51[1:0] sdlyb51[1:0] iledb 51set[3:0] w data for matrix 51(db51) 26h 08h scycb52[1:0] sdlyb52[1:0] iledb 52set[3:0] w data for matrix 52(db52) 27h 08h scycb53[1:0] sdlyb53[1:0] iledb 53set[3:0] w data for matrix 53(db53) 28h 08h scycb54[1:0] sdlyb54[1:0] iledb 54set[3:0] w data for matrix 54(db54) 29h 08h scycb55[1:0] sdlyb55[1:0] iledb 55set[3:0] w data for matrix 55(db55) 2ah 08h scycb56[1:0] sdlyb56[1:0] iledb 56set[3:0] w data for matrix 56(db56) 2bh 08h scycb60[1:0] sdlyb60[1:0] iledb 60set[3:0] w data for matrix 60(db60) 2ch 08h scycb61[1:0] sdlyb61[1:0] iledb 61set[3:0] w data for matrix 61(db61) 2dh 08h scycb62[1:0] sdlyb62[1:0] iledb 62set[3:0] w data for matrix 62(db62) 2eh 08h scycb63[1:0] sdlyb63[1:0] iledb 63set[3:0] w data for matrix 63(db63) 2fh 08h scycb64[1:0] sdlyb64[1:0] iledb 64set[3:0] w data for matrix 64(db64) 30h 08h scycb65[1:0] sdlyb65[1:0] iledb 65set[3:0] w data for matrix 65(db65) technical note 18/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 31h 08h scycb66[1:0] sdlyb66[1:0] iledb66set[3:0] matrix data w data for matrix 66(db66) 32h 08h scycb70[1:0] sdlyb70[1:0] iledb 70set[3:0] w data for matrix 70(db70) 33h 08h scycb71[1:0] sdlyb71[1:0] iledb 71set[3:0] w data for matrix 71(db71) 34h 08h scycb72[1:0] sdlyb72[1:0] iledb 72set[3:0] w data for matrix 72(db72) 35h 08h scycb73[1:0] sdlyb73[1:0] iledb 73set[3:0] w data for matrix 73(db73) 36h 08h scycb74[1:0] sdlyb74[1:0] iledb 74set[3:0] w data for matrix 74(db74) 37h 08h scycb75[1:0] sdlyb75[1:0] iledb 75set[3:0] w data for matrix 75(db75) 38h 08h scycb76[1:0] sdlyb76[1:0] iledb 76set[3:0] w data for matrix 76(db76) 39h 08h scycb80[1:0] sdlyb80[1:0] iledb 80set[3:0] w data for matrix 80(db80) 3ah 08h scycb81[1:0] sdlyb81[1:0] iledb 81set[3:0] w data for matrix 81(db81) 3bh 08h scycb82[1:0] sdlyb82[1:0] iledb 82set[3:0] w data for matrix 82(db82) 3ch 08h scycb83[1:0] sdlyb83[1:0] iledb 83set[3:0] w data for matrix 83(db83) 3dh 08h scycb84[1:0] sdlyb84[1:0] iledb 84set[3:0] w data for matrix 84(db84) 3eh 08h scycb85[1:0] sdlyb85[1:0] iledb 85set[3:0] w data for matrix 85(db85) 3fh 08h scycb86[1:0] sdlyb86[1:0] iledb 86set[3:0] w data for matrix 86(db86) 40h 08h scycb90[1:0] sdlyb90[1:0] iledb 90set[3:0] w data for matrix 90(db90) 41h 08h scycb91[1:0] sdlyb91[1:0] iledb 91set[3:0] w data for matrix 91(db91) 42h 08h scycb92[1:0] sdlyb92[1:0] iledb 92set[3:0] w data for matrix 92(db92) 43h 08h scycb93[1:0] sdlyb93[1:0] iledb 93set[3:0] w data for matrix 93(db93) 44h 08h scycb94[1:0] sdlyb94[1:0] iledb 94set[3:0] w data for matrix 94(db94) 45h 08h scycb95[1:0] sdlyb95[1:0] iledb 95set[3:0] w data for matrix 95(db95) 46h 08h scycb96[1:0] sdlyb96[1:0] iledb 96set[3:0] w data for matrix 96(db96) 47h 08h scycba0[1:0] sdlyba0[1:0] iledba0 set[3:0] w data for matrix a0(dba0) 48h 08h scycba1[1:0] sdlyba1[1:0] iledba1 set[3:0] w data for matrix a1(dba1) 49h 08h scycba2[1:0] sdlyba2[1:0] iledba2 set[3:0] w data for matrix a2(dba2) 4ah 08h scycba3[1:0] sdlyba3[1:0] iledba3 set[3:0] w data for matrix a3(dba3) 4bh 08h scycba4[1:0] sdlyba4[1:0] iledba4 set[3:0] w data for matrix a4(dba4) 4ch 08h scycba5[1:0] sdlyba5 [1:0] iledba5set[3:0] w da ta for matrix a5(dba5) 4dh 08h scycba6[1:0] sdlyba6 [1:0] iledba6set[3:0] w da ta for matrix a6(dba6) 4eh 08h scycbb0[1:0] sdlybb0[1:0] iledbb0 set[3:0] w data for matrix b0(dbb0) 4fh 08h scycbb1[1:0] sdlybb1[1:0] iledbb1 set[3:0] w data for matrix b1(dbb1) 50h 08h scycbb2[1:0] sdlybb2[1:0] iledbb2 set[3:0] w data for matrix b2(dbb2) 51h 08h scycbb3[1:0] sdlybb3[1:0] iledbb3 set[3:0] w data for matrix b3(dbb3) 52h 08h scycbb4[1:0] sdlybb4[1:0] iledbb4 set[3:0] w data for matrix b4(dbb4) 53h 08h scycbb5[1:0] sdlybb5[1:0] iledbb5 set[3:0] w data for matrix b5(dbb5) 54h 08h scycbb6[1:0] sdlybb6[1:0] iledbb6 set[3:0] w data for matrix b6(dbb6) 55h 08h scycbc0[1:0] sdlybc0[1:0] iledbc 0set[3:0] w data fo r matrix c0(dbc0) 56h 08h scycbc1[1:0] sdlybc1[1:0] iledbc 1set[3:0] w data fo r matrix c1(dbc1) 57h 08h scycbc2[1:0] sdlybc2[1:0] iledbc 2set[3:0] w data fo r matrix c2(dbc2) 58h 08h scycbc3[1:0] sdlybc3[1:0] iledbc 3set[3:0] w data fo r matrix c3(dbc3) 59h 08h scycbc4[1:0] sdlybc4[1:0] iledbc 4set[3:0] w data fo r matrix c4(dbc4) 5ah 08h scycbc5[1:0] sdlybc5[1:0] iledbc 5set[3:0] w data fo r matrix c5(dbc5) 5bh 08h scycbc6[1:0] sdlybc6[1:0] iledbc 6set[3:0] w data fo r matrix c6(dbc6) 5ch 08h scycbd0[1:0] sdlybd0[1:0] iledbd 0set[3:0] w data fo r matrix d0(dbd0) 5dh 08h scycbd1[1:0] sdlybd1[1:0] iledbd 1set[3:0] w data fo r matrix d1(dbd1) 5eh 08h scycbd2[1:0] sdlybd2[1:0] iledbd 2set[3:0] w data fo r matrix d2(dbd2) 5fh 08h scycbd3[1:0] sdlybd3[1:0] iledbd 3set[3:0] w data fo r matrix d3(dbd3) 60h 08h scycbd4[1:0] sdlybd4[1:0] iledbd 4set[3:0] w data fo r matrix d4(dbd4) technical note 19/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address default d7 d6 d5 d4 d3 d2 d1 d0 block r/w remark 61h 08h scycbd5[1:0] sdlybd5[1:0] iledbd5set[3:0] matrix data w data for matrix d5(dbd5) 62h 08h scycbd6[1:0] sdlybd6[1:0] iledbd 6set[3:0] w data fo r matrix d6(dbd6) 63h 08h scycbe0[1:0] sdlybe0[1:0] iledbe0 set[3:0] w data for matrix e0(dbe0) 64h 08h scycbe1[1:0] sdlybe1[1:0] iledbe1 set[3:0] w data for matrix e1(dbe1) 65h 08h scycbe2[1:0] sdlybe2[1:0] iledbe2 set[3:0] w data for matrix e2(dbe2) 66h 08h scycbe3[1:0] sdlybe3[1:0] iledbe3 set[3:0] w data for matrix e3(dbe3) 67h 08h scycbe4[1:0] sdlybe4[1:0] iledbe4 set[3:0] w data for matrix e4(dbe4) 68h 08h scycbe5[1:0] sdlybe5[1:0] iledbe5 set[3:0] w data for matrix e5(dbe5) 69h 08h scycbe6[1:0] sdlybe6[1:0] iledbe6 set[3:0] w data for matrix e6(dbe6) 6ah 08h scycbf0[1:0] sdlybf0[1:0] iledbf 0set[3:0] w data for matrix f0(dbf0) 6bh 08h scycbf1[1:0] sdlybf1[1:0] iledbf 1set[3:0] w data for matrix f1(dbf1) 6ch 08h scycbf2[1:0] sdlybf2[1:0] iledbf 2set[3:0] w data for matrix f2(dbf2) 6dh 08h scycbf3[1:0] sdlybf3[1:0] iledbf 3set[3:0] w data for matrix f3(dbf3) 6eh 08h scycbf4[1:0] sdlybf4[1:0] iledbf 4set[3:0] w data for matrix f4(dbf4) 6fh 08h scycbf5[1:0] sdlybf5[1:0] iledbf 5set[3:0] w data for matrix f5(dbf5) 70h 08h scycbf6[1:0] sdlybf6[1:0] iledbf 6set[3:0] w data for matrix f6(dbf6) 71h 08h scycbg0[1:0] sdlybg0[1:0] iledbg 0set[3:0] w data for matrix g0(dbg0) 72h 08h scycbg1[1:0] sdlybg1[1:0] iledbg 1set[3:0] w data for matrix g1(dbg1) 73h 08h scycbg2[1:0] sdlybg2[1:0] iledbg 2set[3:0] w data for matrix g2(dbg2) 74h 08h scycbg3[1:0] sdlybg3[1:0] iledbg 3set[3:0] w data for matrix g3(dbg3) 75h 08h scycbg4[1:0] sdlybg4[1:0] iledbg 4set[3:0] w data for matrix g4(dbg4) 76h 08h scycbg5[1:0] sdlybg5[1:0] iledbg 5set[3:0] w data for matrix g5(dbg5) 77h 08h scycbg6[1:0] sdlybg6[1:0] iledbg 6set[3:0] w data for matrix g6(dbg6) technical note 20/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. register map address 00h < software reset > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h w - - - - - - - sftrst initial value 00h - - - - - - - 0 bit 0 : sftrst software reset ?0? : reset cancel ?1? : reset(all register initializing) *sftrst register return to 0 automatically. address 01h technical note 21/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 12h < led7-12 enable > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 12h w - - led12on led11on led10on led9on led8on led7on initial value 00h 0 0 0 0 0 0 0 0 bit 0 : led7on led7 on/off setting ?0? : led7 off(initial) ?1? : led7 on bit 1 : led8on led8 on/off setting ?0? : led8 off(initial) ?1? : led8 on bit 2 : led9on led9 on/off setting ?0? : led9 off(initial) ?1? : led9 on bit 3 : led10on led10 on/off setting ?0? : led10 off(initial) ?1? : led10 on bit 4 : led11on led11 on/off setting ?0? : led11 off(initial) ?1? : led11 on bit 5 : led12on led12 on/off setting ?0? : led12 off(initial) ?1? : led12 on * current setting follows iledaxxset[3 :0] or iledbxxset[3:0] register. address 13h < led13-17 enable > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 13h w - - - led17on led16on led15on led14on led13on initial value 00h 0 0 0 0 0 0 0 0 bit 0 : led13on led13 on/off setting ?0? : led13 off(initial) ?1? : led13 on bit 1 : led14on led14 on/off setting ?0? : led14 off(initial) ?1? : led14 on bit 2 : led15on led15 on/off setting ?0? : led15 off(initial) ?1? : led15 on bit 3 : led16on led16 on/off setting ?0? : led16 off(initial) ?1? : led16 on bit 4 : led17on led17 on/off setting ?0? : led17 off(initial) ?1? : led17 on * current setting follows iledaxxset[3 :0] or iledbxxset[3:0] register. technical note 22/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 17h < led14-17 tdma enable > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 17h w - - - - led17 tdmaon led16 tdmaon led15 tdmaon led14 tdmaon initial value 0fh 0 0 0 0 1 1 1 1 bit 0 : led14tdmaon tdma control enable setting for led14 ?0? : tdma control for led14 is off led current value is set by iledad0set[3:0] or iled bd0set[3:0] (it changes by the oab [7fh, d1] register). it becomes the setting value of iledad0set [3:0] until scroll reset is carried out by sclrst (2eh, d0) register =?1? after a scroll stop, under scrolling. ?1? : tdma control for led14 is on (initial) bit 1 : led15tdmaon tdma control enable setting for led15 ?0? : tdma control for led15 is off led current value is set by iledae0set[3:0] or iledbe0set[3:0]. (it changes by the oab [7fh, d1] register). it becomes the setting value of iledae0set [3:0] until scroll reset is carried out by sclrst (2eh, d0) register =?1? after a scroll stop, under scrolling. ?1? : tdma control for led15 is on (initial) bit 2 : led16tdmaon tdma control enable setting for led16 ?0? : tdma control for led16 is off led current value is set by iledaf0set[3:0] or iledbf0set[3:0]. (it changes by the oab [7fh, d1] register). it becomes the setting value of iledaf0set [3:0] until scroll reset is carried out by sclrst (2eh, d0) register =?1? after a scroll stop, under scrolling. ?1? : tdma control for led16 is on (initial) bit 3 : led17tdmaon tdma control enable setting for led17 ?0? : tdma control for led17 is off led current value is set by iledag0set[3:0] or iledbg0set[3:0]. (it changes by the oab [7fh, d1] register). it becomes the setting value of iledag0set [3:0] until scroll reset is carried out by sclrst (2eh, d0) register =?1? after a scroll stop, under scrolling. ?1? : tdma control for led17 is on (initial) * the setting change at the time of start (30h, d0 ) register =?1? of this register is prohibition. * led, which is set to ?0?(tdma off), is put on and not controlled by sync terminal however syncon (21h,d2) register is set to ?1?. * please use this register only in the following combination. led17tdmaon led16tdmaon led15tdmaon led14tdmaon 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 except the above: prohibition technical note 23/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 20h < led1-17 pwm setting > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 20h w - - pwmset [5:0] initial value 00h 0 0 0 0 0 0 0 0 bit 5-0 : pwmset[5:0] led1-17 pwm duty setting ?000000? : 0/63 0%(initial) ?000001? : 1/63 1.59% ?100000? : 32/63 50.8% ?111110? : 62/63 98.4% ?111111? : 63/63 100% *please refer to description of operation, chapter 2 address 21h < sync operation control > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 21h w - - - - syncact syncon clkout clkin initial value 00h 0 0 0 0 0 0 0 0 bit 0 : clkin selection clk for pwm control ?0? : internal osc (initial) ?1? : external clk input bit 1 : clkout output clk enable ?0? : clk is not output (initial) ?1? : output selected clk from clkout pin as for clkin & clkout, setting change is fo rbidden under oscen (01h, d3) register =?1? and also under clock input to clkin term inal. bit 2 : syncon sync operation enable ?0? : disable sync operation (initial) ?1? : sync pin control led driver on/off bit 3 : syncact sync operation setting ?0? : when sync pin is ?l?, led drivers are on (initial) ?1? : when sync pin is ?h?, led drivers are on address 2dh < pwm, slope, scroll on/off setting > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 2dh w - - - - - pwmen slpen sclen initial value 00h 0 0 0 0 0 0 0 0 bit 0 : sclen scroll operation on/off setting ?0? : scrol operation off(initial value) ?1? : scrol operation on bit 1 : slpen slope operation on/off setting ?0? : slope operation off(initial value) ?1? : slope operation on bit 2 : pwmen pwm control at led1-17 on/off setting ?0? : pwm operation is invalid(initial value) ?1? : pwm operation is valid *please refer to description of operation, chapter 2 technical note 24/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 2eh < reset scroll > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 2eh w - - - - - - - sclrst initial value 00h 0 0 0 0 0 0 0 0 bit 0 : sclrst reset scroll state ?0? : not reset(initial value) ?1? : reset scroll state * sclrst register return to 0 automatically address 2fh < scroll setting > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 2fh w - sclspeed [2:0] up down right left initial value 00h 0 0 0 0 0 0 0 0 bit 0 : left setting the scroll operation from right to left ?0? : scroll operation off (initial value) ?1? : scroll operation on bit 1 : right setting the scroll operation from left to right ?0? : scroll operation off (initial value) ?1? : scroll operation on *when left operation is valid, right setting is ignored. bit 2 : down setting the scroll operation from top to bottom ?0? : scroll operation off (initial value) ?1? : scroll operation on bit 3 : up setting the scroll operation from bottom to top ?0? : scroll operation off (initial value) ?1? : scroll operation on *when up operation is valid, down setting is ignored. bit 6-4 : sclspeed[2:0] setting the scroll speed ?000? : 0.1s (initial value) ?001? : 0.2s ?010? : 0.3s ?011? : 0.4s ?100? : 0.5s ?101? : 0.6s ?110? : 0.7s ?111? : 0.8s *setting time is based on osc frequency, and the above-mentioned shows the value under typ (1.2mhz). *setting time changes on clkin terminal input frequency at the external clock operation. example) clkin input frequency=1.2mhz ?000?: 0.1sec (it is the same as the above) clkin input frequency=2.4mhz ?000?: 0.05sec clkin input frequency= 0.6mhz ?000?: 0.2sec address 30h < led matrix control > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 30h w - - - - - - - start initial value 00h 0 0 0 0 0 0 0 0 bit 0 : start lighting/turning off bit of matrix led(led1-17) ?0? : matrix led(led1-17) lights out ?1? : matrix led(led1-17) lighting, slope and scroll sequence start technical note 25/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 31h < matrix data clear > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 31h w - - - - - - clrb clra initial value 00h 0 0 0 0 0 0 0 0 bit 0 : clra reset a-pattern register ?0? : a-pattern register is not reset and writable(initial value) ?1? : a-pattern re gister is reset bit 0 : clrb reset b-pattern register ?0? : b-pattern register is not reset and writable(initial value) ?1? : b-pattern re gister is reset *clra and clrb register return to 0 automatically. address 7fh < register map change > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7fh w - - - - - iab oab rmcg initial value 00h 0 0 0 0 0 0 0 0 bit 0 : rmcg change register map ?0? : control register is selected(initial value) ?1? : a-pattern register or b-pattern register is selected bit 1 : oab select register to output for matrix ?0? : a-pattern register is selected(initial value) ?1? : b-pattern regi ster is selected bit 2 : iab select register to write matrix data ?0? : a-pattern register is selected(initial value) ?1? : b-pattern regi ster is selected * it is prohibition to write a-pattern data when a-pattern is displaying (oab=0). also, it is prohibition to write b-pattern data when b-pattern is displaying (oab=1). change of a display picture should be done by change of the oab register, after updating of a non-displaying pattern register. technical note 26/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 01h-77h < a-pattern register data > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01-77h w scycaxx [1:0] sdlyax x [1:0] iledaxxset [3:0] initial value 08h 0 0 0 0 1 0 0 0 bit 3-0 : iledaxxset[3:0] led output current setting for a-pattern matrix data ?0000? : 0.00ma ?0001? : 1.33ma ?0010? : 2.67ma ?0011? : 4.00ma ?0100? : 5.33ma ?0101? : 6.67ma ?0110? : 8.00ma ?0111? : 9.33ma ?1000? : 10.67ma(initial value) ?1001? : 12.00ma ?1010? : 13.33ma ?1011? : 14.67ma ?1100? : 16.00ma ?1101? : 17.33ma ?1110? : 18.67ma ?1111? : 20.00ma bit 5-4 : sdlyaxx[1:0] slope delay setting for a-pattern matrix ?00? : no delay(initial value) ?01? : 1/4x(slope cycle time) ?10? : 1/2x(slope cycle time) ?11? : 3/4x(slope cycle time) bit 7-6 : scycaxx[1:0] slope cycl e time setting for a-pattern matrix ?00? : no slope control(initial value) ?01? : 1s(=slope cycle time) ?10? : 2s(=slope cycle time) ?11? : 3s(=slope cycle time) * the ?xx? shows the matrix number from ?00? to ?g6?. please refer 7x17 led matrix coordinate. *setting time is based on osc frequency, and the above-mentioned shows the value under typ (1.2mhz). *setting time changes on clkin terminal input frequency at the external clock operation. example) clkin input frequency=1.2mhz ?01?: slope cycle =1sec (it is the same as the above) clkin input frequency=2.4mhz ?01?: slope cycle =0.5sec clkin input frequency=0.6mhz ?01?: slope cycle =2sec technical note 27/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. address 01h-77h < b-pattern register data > address (index) r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01-77h w scycbxx[1:0] sdlybxx[1:0] iledbxxset[3:0] initial value 08h 0 0 0 0 1 0 0 0 bit 3-0 : iledbxxset[3:0] led output current setting for b-pattern matrix data ?0000? : 0.00ma ?0001? : 1.33ma ?0010? : 2.67ma ?0011? : 4.00ma ?0100? : 5.33ma ?0101? : 6.67ma ?0110? : 8.00ma ?0111? : 9.33ma ?1000? : 10.67ma(initial value) ?1001? : 12.00ma ?1010? : 13.33ma ?1011? : 14.67ma ?1100? : 16.00ma ?1101? : 17.33ma ?1110? : 18.67ma ?1111? : 20.00ma bit 5-4 : sdlybxx[1:0] slope delay setting for b-pattern matrix ?00? : no delay(initial value) ?01? : 1/4x(slope cycle time) ?10? : 1/2x(slope cycle time) ?11? : 3/4x(slope cycle time) bit 7-6 : scycbxx[1:0] slope cycl e time setting for b-pattern matrix ?00? : no slope control(initial value) ?01? : 1s(=slope cycle time) ?10? : 2s(=slope cycle time) ?11? : 3s(=slope cycle time) * the ?xx? shows the matrix number from ?00? to ?g6?. please refer 7x17 led matrix coordinate. *setting time is based on osc frequency, and the above-mentioned shows the value under typ (1.2mhz). *setting time changes on clkin terminal input frequency at the external clock operation. example) clkin input frequency=1.2mhz ?01?: slope cycle =1sec (it is the same as the above) clkin input frequency=2.4mhz ?01?: slope cycle =0.5sec clkin input frequency=0.6mhz ?01?: slope cycle =2sec technical note 28/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. description of operation 1. led matrix 1-1. lighting method of dot matrix it can control 7 x 17 matrix. fig.10 7 x 17 led matrix coordinate the sw1 ? sw7 is turned on by serial. led is driven one by one within the on period. fig.11 sw timing 00 10 20 30 40 50 60 70 80 90 a0 b0 c0 d0 e0 f0 g0 01 11 21 31 41 51 61 71 81 91 a1 b1 c1 d1 e1 f1 g1 02 12 22 32 42 52 62 72 82 92 a2 b2 c2 d2 e2 f2 g2 03 13 23 33 43 53 63 73 83 93 a3 b3 c3 d3 e3 f3 g3 04 14 24 34 44 54 64 74 84 94 a4 b4 c4 d4 e4 f4 g4 05 15 25 35 45 55 65 75 85 95 a5 b5 c5 d5 e5 f5 g5 06 16 26 36 46 56 66 76 86 96 a6 b6 c6 d6 e6 f6 g6 vinsw tdma led17 tdma led1 tdma led2 sw 1 t00 sw 7 t 06 sw 2 t01 sw 3 t02 sw 4 t03 sw 5 t04 sw 6 t05 tdma led3 tdma led4 tdma led5 tdma led6 tdma led7 tdma led8 tdma led9 tdma led10 tdma led11 tdma led12 tdma led13 tdma led14 tdma led15 tdma led16 sw4 sw2 sw5 sw3 sw1 1/7tdma period 680clk @1.2mhz 566.67us sw6 sw7 led1 pwm period 635clk @1.2mhz 529.2us duty is variable 0/63 and between 1/63 and 63/63 of pwm period. dag0 dag6 dag0 led17 dag5 dag4 dag3 dag2 dag1 da00 da06 da00 da05 da04 da03 da02 da01 n5n5n5n5n5 tdma period 4760clk @1.2mhz 3.97ms dag3 dag2 da03 da02 technical note 29/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 1-2. led lighting example the firefly lighting example. the following command set is the example of led matrix firefly lighting. it can control the turn on/off time in detail by slope setting registers. 1) 7fh 00000000 select control register 2) 21h 00000000 select internal osc for clk 3) 01h 00001000 start osc 4) 11h 00111111 set led1-6 enable 5) 12h 00111111 set led7-12 enable 6) 13h 00011111 set led13-17 enable 7) 20h 00111111 set max duty at slope 8) 1fh 00000001 select a-pattern or b-pattern register, select a-pattern register to write matrix data 9) 01-77h xxxxxxxx write a-pattern data 10) 7fh 00000000 select control register, select a-pattern register to output for matrix 11) 2dh 00000100 set slope control enable 12) 30h 00000001 start slope sequence 13) 30h 00000000 lights out technical note 30/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 2. led driver current, slope and scroll sequence control 2-1. led driver current control it can be controlled pwm duty and dc current for led driver current. item control object control detail setting registers name * bits (a) pwm duty whole matrix 0/63~63/63 (64 step) pwmset 6 (b) dc current each matrix dot 0~20.00ma (16 step) iledaxxset iledbxxset 4 * the ?xx? shows the matrix number from ?00? to ?g6?. please refer 7x17 led matrix coordinate. ~ 680clk = 1/7tdma ~ ~ (a) pwm duty minimum width=5clk ~ duty is variable by pwmset[5 0] or slope control between 0/63 and 63/63. duty 1/63=10clk clk (ex.1.2mhz at internal osc) led drive internal enable signal off fig.12 led output current timing and pwm cycle 635clk of pwm period is set in the 1/7 tdma period (680clk). pwm is operated 63 steps of 10clk. tdma period is 3.97s (@1.2mhz). moreover, it has the starting waiting time of a constant current driver by 5clk(s). pwm?h? time turns into on time after waiting 5 clk. (however, led driver is set ?off? compulsorily at pwm=0% setting.) fig.13 led output current timing and a pwm cycle pwm = 0/63 setting 0ma pwm = 1/63 setting 5clk 1/63 = 10clk 5clk 2/63 = 20clk pwm = 2/63 setting off led drive internal enable signal 5clk wait technical note 31/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 2-2. slope control it can be controlled delay and slope cycle time for led driver current. item control object control detail setting registers name * bits (a) delay each matrix dot 0~3/4 x slope cycle time (4 step) sdlyaxx sdlybxx 2 (b) slope cycle time each matrix dot 0~3sec (4 step) scycaxx scycbxx 2 * the ?xx? shows the matrix number from ?00? to ?g6?. please refer 7x17 led matrix coordinate. slope 3 100% slope 1 slope 2 slope 4 (a) delay pwm duty repeat slope 1-4 start 0% time (b) slope cycle time 1/4 of slope cycle time fig.14 slope operation when slpen=?1? and pwmen=sclen=?0?, slope operation starts (like upper figure). after ?delay? time slope1-4 operation repeat. each period of slope1-4 is 1/4 of slope cycle time. slope 1: 1 step is 1/63 of slope 1 period. duty is increased 1.587% step by step. slope 2: duty is fixed at 100%. slope 3: 1 step is 1/63 of slope 1 period. duty is decreased 1.587% step by step. slope 4: duty is fixed at 0%. technical note 32/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 2-3. scroll control 2-3-1 normal operation 2-3-2 operation at tdma off setting (the following is the matrix arrangement which has not assigned led16-led17.) left scroll right scroll up scroll tdma off tdma off a-pattern data b-pattern data a-pattern data b-pattern data down scroll left scroll right scroll up scroll down scroll technical note 33/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 2-4. relation of pwm, slope and scroll control register of condition and enable pwm slope scroll condition pwmset [5:0] scycxxx [1:0] sdlyxxx [1:0] sclspeed [2:0] up/down/right/left enable pwmen slpen sclen combination of command operation pwmen slpen sclen 1 off off off 2 on off off 3 off on off 4 on on off 5 off off on do not use this combination on off on off on on on on on 100% pw m duty start 0% tim e 100% pw m duty start 0% time duty set at pw mset[5:0] 0/63 63/63 100% delay pw m duty start 0% tim e slope c y cle time 100% delay pw m duty start 0% tim e slope cycle time duty set at pw mset[5:0] 0/63 63/63 100% pwm duty start 0% time operation 1 operation 2 operation 3 operation 4 operation 5 technical note 34/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 3. power up sequence command v io resetb vbat t vbaton1 t vbatoff1 t vioon=min 0.5ms t rstb=min 0.1ms possible t rst=min 0ms t viooff=min 1ms vinsw t vinsw on t vbaton2 t vbatoff2 t vinsw off inhibit inhibit fig.15 power up sequence please take sufficient wait time for each power/control signal. however, if vbat<2.1v(typ) or ta >t tsd (typ:175 ), the command input is not effective because of the protection operation 4. reset there are two kinds of reset, software reset and hardware reset (1)software reset ? all the registers are initialized by sftrst=?1?. ? sftrst is an automatically returned to ?0?. (auto return 0). (2)hardware reset ? it shifts to hardware reset by changing resetb pin ?h? ?l?. ? the condition of all the registers under hardware reset pin is returned to the initial value and it stops accepting all address.all led driver turn off. ? it?s possible to release from a state of hardware reset by changing resetb pin ?l? ?h?. resetb pin has delay circuit. it doesn?t recognize as hardware reset in ?l? period under 5 s. 5. thermal shutdown a thermal shutdown function is effective at all blocks of those other than vref. return to the state before detection automatically at the time of release. the thermal shutdown function is detection temperature that it works is about 175 detection temperature has a hysteresis, and detection release temperature is about 150 (design reference value) 6. uvlo function (vbat voltage low-voltage detection) uvlo function is effective at all blo cks of those other than vref, and when det ected, those blocks function is stopped. return to the state before detection automatically at the time of release. technical note 35/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 7. i/o when the resetb pin is low, the input buffers (sda and scl) are disabling for the low consumption power. level shift vbat scl (sda) resetb logic vio en resetb=l, output ?h? fig.16 input disabling by resetb 8. standard clock input and output it is possible to carry out synchronous operation of two or more ics using the input-and-output function of a standard clock. fig.17 i/o part equivalent circuit diagram ? when a clock is supplied from the exterior inputting an external standard clock from clkin and setting register clkin=1, ic operates with the clock inputted from clkin as a standard clock. ? when the built-in oscillation circuit of one ic is used when a clock cannot be supplied from the exterior, it is possible to synchronize between ics by the connection as the following figure. fig.18 it is an example of application for the usage of two or more. osc clkout clkin ic1 osc clkout clkin ic2 osc clkout clkin ic3 when a clock is strung osc clkout clkin ic1 osc clkout clkin ic2 osc clkout clkin ic3 when a clock is supplied from ic1 sel register : clkout sync clkin clkout register: syncon register : clkin tdma controller osc pmos switch led driver led matrix technical note 36/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. 9. external on/off synchronization (sync terminal) lighting of led that synchronized with the external signal is possible. by setting h/l of sync terminal, led drivers output is set on/off. it?s asynchronous operation with the internal tdma control. fig.19 i/o part equivalent circuit diagram 10. about terminal processing of the function which is not used please set up a test terminal and the unused terminal as the following table. especially, if an input terminal is not fixed, it may occur the unstable state of a device and the unexpected internal current. terminal name processing reason sync gnd short the input terminal clkin gnd short the input terminal clkout open the output terminal test1 ? test5 gnd short the input terminal for a test testo open the output terminal for a test do open the output terminal led terminal gnd short in order to avoid an unfixed state. (a register setup in connection with led terminal that is not used is forbidden.) sw terminal vinsw short in order to avoid an unfixed state. (a register setup in connection with sw terminal that is not used is forbidden.) sel register : clkout sync clkin clkout register : syncon register : clkin tdma controller osc pmos switch led driver led matrix technical note 37/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. pcb pattern of the power dissipation measuring board 1 st layer(component) 2 nd layer 3 rd layer 4 th layer 5 th layer 6 th layer 7 th layer 8 th layer(solder) technical note 38/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. notes for use (1) absolute ma ximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) power supply and ground line design pcb pattern to provide low impedance for the wiring between the power supply and the ground lines. pay attention to the interference by common impedance of layout pattern when there are plural power supplies and ground lines. especially, when there are ground pattern for small signal and ground pattern for large current included the external circuits, please separate each ground pattern. furthermore, for all power supply pins to ics, mount a capacitor between the power supply and the ground pin. at the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) ground voltage make setting of the potential of the ground pin so that it will be maintained at the minimum in any operating state. furthermore, check to be sure no pins are at a potential lower than the ground voltage including an actual electric transient. (4) short circuit between pins and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occurs due to foreign matters entering between pins or between the pin and the power supply or the ground pin, the ics can break down. (5) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. (6) input pins in terms of the construction of ic, parasitic elements are inevitably formed in relation to potential. the operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input pin. therefore, pay thorough attention not to handle the input pins, such as to apply to the input pins a voltage lower than the ground respectively, so that any parasitic element will operate. furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the ic. in addition, even if the power supply voltage is applied, apply to the input pins a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to dc bias and changes in the capacitance due to temperature, etc. (8) thermal shutdown circuit (tsd) this lsi builds in a thermal shutdown (tsd) circuit. when ju nction temperatures become detec tion temperature or higher, the thermal shutdown circuit operates and turns a switch off. the thermal shutdown circuit, which is aimed at isolating the lsi from thermal runaway as much as possible, is not ai med at the protection or guarantee of the lsi. therefore, do not continuously use the lsi with this circuit operating or use the lsi assuming its operation. (9) thermal design perform thermal design in which there are adequate margins by taking into account the permissible dissipation (pd) in actual states of use. (10) about the pin for the test, the un-use pin prevent a problem from being in the pin for the test and the un-use pin under the state of actual use. please refer to a function manual and an application notebook. and, as for the pin that doesn't specially have an explanation, ask our company person in charge. (11) about the rush current for ics with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of wiring. (12) about the function description or application note or more. the function description and the application notebook are the design materials to design a set. so, the contents of the materials aren't always guaranteed. please design application by having fully examination and evaluation include the external elements. technical note 39/39 bd26502gul www.rohm.com 2010.02 - rev.a ? 2010 rohm co., ltd. all rights reserved. ordering part number b d 2 6 5 0 2 g u l - e 2 part no. part no. package gul : vcsp50l4 packaging and forming specification e2: embossed tape and reel (unit : mm) vcsp50l4 (bd26502gul) 0.06 s s a b ba 0.05 8 b 5 4.100.05 p=0.57 4 6 d 62-0.250.05 h 3 0.30.05 0.10.05 g a 2 p=0.57 0.55max 7 c f (0.15)index post 4.100.05 1 0.30.05 1pin mark e ? order quantity needs to be multiple of the minimum quantity. r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. |
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